Monday, October 8, 2012

IEEE VLSI POWER ELECTRONICS, CRYPTOGRAPHY, SIGNAL PROCESSING PROJECTS


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2012 IEEE VLSI PROJECT TITLES
IMAGE PROCESSING
Cognition and Removal of Impulse Noise With Uncertainty
Fast Higher-Order MR Image Reconstruction Using Singular-Vector Separation
Image Deblurring Using Derivative Compressed Sensing for Optical Imaging Application
New Families of Fourier Eigen functions for Steerable Filtering
Scalable Coding of Encrypted Images
A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform
Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA
Chaos-Based Security Solution for Fingerprint Data During Communication and Transmission
An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion
Interference Removal Operation for Spread Spectrum Fingerprinting Scheme
Robust Watermarking of Compressed and Encrypted JPEG2000 Images
Spread Spectrum Magnetic Resonance Imaging
VLSI Architecture of Arithmetic Coder Used in SPIHT
ARITHMETIC CORES
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
Optimizing Floating Point Units in Hybrid FPGAs
Low-Power and Area-Efficient Carry Select Adder
COMMUNICATION SYSTEMS
A Highly-Integrated 3–8 GHz Ultra-Wideband RF Transmitter With Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control
High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm
Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding
Power Management of MIMO Network Interfaces on Mobile Systems
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction
A Fourier Based Method for Approximating the Joint Detection Probability in MIMO Communications
Low Complexity Transmitter Architectures for SFBC MIMO-OFDM Systems
On the Reduction of Additive Complexity of Cyclotomic FFTs
A Mutual Distortion and Impairment Compensator for Wideband Direct-Conversion Transmitters Using Neural Networks
Segmentation of Source Symbols for Adaptive Arithmetic Coding
Cooperative Beam forming for Cognitive Radio Networks-A Cross-Layer Design
Dynamic Resource Allocation in MIMO-OFDMA Systems with Full-Duplex and Hybrid Relaying
Good Synchronization Sequences for Permutation Codes
Low Latency Coding- Convolutional Codes vs LDPC Codes
Low-Complexity Iterative Channel Estimation for Turbo Receivers
Spectrum Sensing in the Presence of Multiple Primary Users
The Design of Hybrid Asymmetric-FIR Analog Pulse-Shaping Filters Against Receiver Timing Jitter
Uncoordinated Beam forming for Cognitive Networks
3D MIMO-OFDM Channel Estimation
Interleaved Product LDPC Codes
Secure Communication in the Low-SNR Regime
Blind Signal Processing for Impulsive Noise Channels
Curvature Based ECG Signal Compression for Effective Communication on WPAN
Distributed Coordination Protocol for Ad Hoc Cognitive Radio Networks
A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter
A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX
A Novel Filter-Bank Multicarrier Scheme to Mitigate the Intrinsic Interference Application to MIMO Systems
Differential Coding for MAC Based Two-User MIMO Communication Systems
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
New S-BandBand pass Filter (BPF) With Wideband Passband for Wireless Communication Systems
Transmission of 4-ASK Optical Fast OFDM With Chromatic Dispersion Compensation
VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter
A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter
AUDIO/SPEECH SIGNAL PROCESSING
Enhancement of Single-Channel Periodic Signals in the Time-Domain
Multi-View and Multi-Objective Semi-Supervised Learning for HMM-Based Automatic Speech Recognition
Musical-Noise-Free Speech Enhancement Based on Optimized Iterative Spectral Subtraction
Robustness and Regularization of Personal Audio Systems
Speaker and Noise Factorization for Robust Speech Recognition
State-Space Frequency-Domain Adaptive Filtering for Nonlinear Acoustic Echo Cancellation
Vocal Tract Length Normalization for Statistical Parametric Speech Synthesis
A Dual-Channel Time-Spread Echo Method for Audio Watermarking
A Low-Complexity Design for an MP3 Multi-Channel
Telephone Channel Compensation in Speaker Verification Using a Polynomial Approximation in the Log-Filter-Bank Energy Domain
Enhancement of Residual Echo for Robust Acoustic Echo Cancellation
A Wiener Filter Approach to Microphone Leakage Reduction in Close-Microphone Applications
CRYPTOGRAPHY TECHNIQUES
Efficient FPGA Implementations of Point Multiplication on Binary Edwards & Generalized Hessian Curves Using
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes
Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes
A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits
SIGNAL PROCESSING
A Highly-Digital VCO-Based ADC Using Phase Interpolator & Digital Calibration
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier
Resource-Efficient FPGA Architecture and Implementation of Hough Transform
A Low-Power Low-Cost Design of Primary Synchronization Signal Detection
A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers
Hardware Implementation of Nakagami and Weibull Variate Generators
Pipelined Parallel FFT Architectures via Folding Transformation
A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS-LMS Adaptive Filter
A Single-Pass-Based Localized Adaptive Interpolation Filter for Video Coding
An Optimization-Based Parallel Particle Filter for Multitarget Tracking
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing
Non-Causal Time-Domain Filters for Single-Channel Noise Reduction
On the BIBO Stability Condition of Adaptive Recursive FLANN Filters With Application to Nonlinear Active Noise Control
Pipelined Parallel FFT Architectures via Folding Transformation
The Design of Hybrid Symmetric-FIR_Analog Pulse-Shaping Filters
Universal Switching FIR Filtering
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic
Fixed-Point Implementation of Cascaded Forward–Backward Adaptive Predictors
Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type-3
POWER ELECTRONICS
Design and Implementation of a New Multilevel Inverter Topology
Digital Filters for Fast Harmonic Sequence Component Separation 3Ph
Spread Spectrum Modulation by Using Asymmetric-Carrier Random PWM
A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic
A Filter Bank and a Self-Tuning Adaptive Filter for the Harmonic and Inter harmonic Estimation in Power Signals
A Shifted SVPWM Method to Control DC-Link Resonant Inverters and Its FPGA Realization
Fully FPGA-Based Sensorless Control for Synchronous AC Drive Using an Extended Kalman Filter
Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators
Time-Domain Design of Digital Compensators for PWM DC-DC Converters (S/H)
Optimal State-Feedback Control of Bilinear DC-DC Converters With Guaranteed Regions of Stability (S/H)
Nonisolated ZVZCS Resonant PWM DC-DC Converter for High Step-Up and High-Power Applications (S/H)
Modified Soft-Switched Three-Phase Three-Level DC-DC Converter for High-Power Applications Having Extended Duty Cycle Range (S/H)
Duty Cycle Exchanging Control for Input-Series-Output-Series Connected Two PS-FB DC-DC Converters (S/H)
Double-Input Converters Based on H-Bridge Cells: Derivation, Small-Signal Modeling, and Power Sharing Analysis (S/H)
Design and Performance of a Bidirectional Isolated DC-DC Converter for a Battery Energy Storage System(S/H)
DC Link Active Power Filter for Three-Phase Diode Rectifier (S/H)
Analysis of PWM Z-Source DC-DC Converter in CCM for Steady State (S/H)
An Active Current Reconstruction and Balancing Strategy With DC-Link Current Sensing for a Multi-phase Coupled-Inductor Converter (S/H)
A Voltage-Controlled PFC Cuk Converter-Based PMBLDCM Drive for Air-Conditioners (S)
A Novel Single-Stage High-Power-Factor AC-to-DC LED Driving Circuit With Leakage Inductance Energy Recycling (S/H)
A Novel Loaded-Resonant Converter for the Application of DC-to-DC Energy Conversions (S/H)
A New Control Approach Based on the Differential Flatness Theory for an AC/DC Converter Used in Electric Vehicles (S)
A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS (S/H)
An Improved Pulse Width Modulation Method for Chopper-Cell-Based Modular Multilevel Converters (S/H)
Average Inductor Current Sensor for Digitally Controlled Switched-Mode Power Supplies (S/H)
Coupling Effect Reduction of a Voltage-Balancing Controller in Single-Phase Cascaded Multilevel Converters (S/H)
Digitally Implemented Average Current-Mode Control in Discontinuous Conduction Mode PFC Rectifier (S/H)
Multilayer Control for Inverters in Parallel Operation Without Intercommunications (S/H)
No-Load Power Reduction Technique for AC or DC Adapters (S/H)
Positive Feed-Forward Control Scheme for Distributed Power Conversion System With Multiple Voltage Sources (S)
Two-Switch Dual-Buck Grid-Connected Inverter With Hysteresis Current Control (S)
A Low-Power AC-DC Single-Stage Converter With Reduced DC Bus Voltage Variation(S/H)
A Resonant Controller With High Structural Robustness for Fixed-Point Digital Implementations (S/H)
DC-DC Converter With Digital Adaptive Slope Control in Auxiliary Phase for Optimal Transient Response and Improved Efficiency (S/H)
Note: S- SIMULATION
MISCELLANEOUS SYSTEM
Dual-Layer Adaptive Error Control for Network-on-Chip Links
Return Data Interleaving for Multi-Channel Embedded CMPs Systems
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
Viterbi-Based Efficient Test Data Compression